Implementation of CPRI protocol in digital repeater based on FPGA

introduction

With the development of mobile communications. The coverage of communication networks has become an important criterion for measuring the operation of communication networks, which directly affects the economic benefits of operators. The development and application of repeaters has become one of the main means to improve the network quality of operators, solve the problem of network blind spots or weak spots, and enhance network coverage. A base station can be connected to several repeaters, and can form a flexible topology structure such as chain, star, tree, etc., which greatly increases the coverage of the base station. At the same time, it not only saves space, but also reduces costs, and improves the efficiency of networking.

However, because there is no unified protocol specification between the traditional analog repeater equipment, it cannot meet the compatibility between system manufacturers and repeater manufacturers, and it is impossible to achieve more effective intercommunication between the base station and the repeater, thereby limiting the control and control between the two. Reliable transmission of data. In 2003, CPRI (Common Public RADIo Interface) interface was jointly developed by five major groups including Ericsson, Huawei, NEC, Nortel Networks and Siemens. The main purpose of the establishment of the organization is to develop a standard protocol for this interface, so that the interface becomes a publicly available indicator. The open CPRI interface provides convenience for 3G base station products and 2G digital repeaters to increase efficiency and increase flexibility.

1 CPRI protocol overview

The CPRI specification defines two layers of protocols, the physical layer and the link layer, which can realize the time-division multiplexing of digital baseband IQ signal transmission. The protocol structure is shown in Figure 1. The physical layer uses the Gigabit Ethernet standard, and the transmitted data adopts 8 B / 10 B encoding and decoding, and is sent serially through the optical module. In order to achieve the required flexibility and cost efficiency, the line bit rate is *. There are three kinds of 4 Mb / s, 1228.8 Mb / s and 2 457.6 Mb / s. The link layer defines a synchronized frame structure. The frame structure includes basic frame and super frame. The frame frequency of each basic frame is 3.84 MHz, including 16 time slots. The size of each time slot is 1 B according to the line bit rate. 2 B, 4 B. The first time slot is a control time slot, and the remaining 15 time slots are I / O data time slots, which are used to transmit I / O data streams. The super frame is composed of 256 basic frames, and the control slots of the 256 basic frames together constitute the control structure of the super frame (as shown in FIG. 2). At the same time, fast C / M channels (Ethernet) and slow C are defined / M channel (HDLC), used to transmit control and management data, and can maintain the repeater.

2 Hardware implementation plan

2.1 Scheme comparison

For CPRI hardware implementation solutions, there are several options to choose from:

(1) PMC scheme. Using PMC7830 or PMC7832 chip, this type of chip integrates all CPRI protocols inside the chip, leaving only the interface, simple and convenient to use, and can fully support the public radio frequency interface (CPRI) specification for wireless base station connection.

(2) The FPGA with ROCKET IO is used to implement the CPRI protocol. This method has high flexibility, but the development time period is relatively long, affecting product development.

(3) The combination of FPGA and SCAN25100. FPGA realizes CPRI's deframing and related interface design, SCAN25100 is responsible for completing 8 B / 10 B codec and high-speed serial-parallel conversion. The link layer frame protocol is easy to modify, while the physical layer is completed by the chip, which is simple to use and stable in performance. The development cost is low and the scalability is good.

(4) The combination of FPGA and TLK4015. TLK4015 is a 4-channel, 0.6-1.5 Gb / s channel transceiver. When the system requires many channels, using this solution can reduce the size of the circuit board.

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