The PIC series of microcontrollers is a high-performance, cost-effective 8-bit embedded controller from Microchip Technology. It uses a reduced instruction set computer (RISC) and a Harvard dual bus and two levels. Instruction pipeline structure. With high speed, low working voltage, low power consumption and other excellent performance and price ratio, PIC series single-chip microcomputers are increasingly favored by MCU development and application engineering technicians. The unique architecture and interrupt resources of the series make it a lot different from other microcontrollers in use. The PIC16CXX series of microcontrollers are taken as an example to introduce the interrupt resource characteristics and application methods of PIC series microcontrollers.
2 Development and blocking of interrupt resources
Figure 1 shows the interrupt logic circuit diagram of PIC16C64/64A/65/65A. The interrupt resources of other models are basically the same, but the resources are different, but there is only one interrupt entry (the entry address is 004H). The interrupts of PIC microcontrollers can be roughly divided into two categories.
The first type is the interrupt directly controlled by the interrupt controller INTCON, including the RB port level change interrupt of the external pin interrupt INT and the timer TMRO overflow interrupt. Their interrupt enable bits and interrupt flags are in the INTCON register. Pin interrupt INT and timer TMRO overflow interrupt are the same as other microprocessors. The RB port level change interrupt is a unique interrupt of the PIC microcontroller. When the RB port high 4-bit I/O line is set as an input, as long as the level of the 4-bit I/O line changes, it will cause an interrupt. The level interrupt feature of the RB port is very useful to the user. Users can directly use the key parts of these lines for level detection, and can use interrupts for protection control. On the other hand, the level interrupt feature can also use the RB port software to control the weak pull-up characteristics to form a matrix keyboard. And use the button to wake up the CPU, which is especially useful for battery-powered systems.
The other type is peripheral interface interrupts, including timer TMR1 overflow interrupt, TMR overflow or match interrupt, synchronous serial port interrupt, asynchronous serial port interrupt, parallel slave interrupt and CCP (Capture/Compare/PWM) interrupt. The PIC16C7X family of microprocessors with A/D capability also has an A/D conversion completion interrupt. The enable bits for these interrupts are in the PIE1 and PIE2 registers, respectively, and the interrupt flags are in PIR1 and PIR2, respectively.
All interrupts have their own interrupt enable bits and interrupt flags. The peripheral interface interrupts are not only controlled by their respective interrupt enable bits, but are also controlled by the peripheral interrupt control enable bits. The global interrupt enable bit GID can control all interrupts. Regardless of the global interrupt enable bit GIE and the corresponding interrupt enable bit state, each interrupt flag bit will be set as long as the interrupt condition is met.
Unlike other microprocessors: When the CPU responds to an interrupt, the global interrupt allows the GIF to be automatically cleared. The interrupt flag bit cannot be cleared by hardware and can only be cleared by software. When the interrupt return instruction RETFIE is executed, the global The interrupt enable bit GIE will be automatically set to re-open the interrupt. Therefore, the relevant interrupt flag bits should be cleared by software before re-opening the interrupt to avoid repeated interrupt requests due to constant interrupt requests. Since the global interrupt enable bit GIE is automatically set by the interrupt service routine (RETFIE instruction), it is not reliable to clear the GIE with software. This is especially important. Use the following procedure to ensure that the entire interrupt is disabled.
***************LOOP BCF INTCON, GIE; disables the entire interrupt BTFSC INTCON, GIE; determines whether the global interrupt is disabled GOTO LOOP; no, resets again... Continue *** ************
For external interrupt events, such as INT pin interrupt and RB port pin change interrupt, etc. are edge triggered, therefore, the external signal requirements of the CPU in response to the interrupt are not critical. In general, the time taken for an interrupt requires 3 or 4 instruction cycles, and the exact time depends on the time at which the interrupt event occurs, regardless of the number of cycles of the instruction itself.
3 priority of the interruptThe PIC series MCU has only one interrupt entry (004H). All interrupts enter the interrupt service subroutine through this entry. As for which interrupt source, the interrupt flag can be acknowledged only after entering the interrupt service subroutine. The microcontroller does not specify the priority of the interrupt, nor does it have a register for setting the interrupt priority. The priority of the interrupt is determined by the order in which the interrupt service subroutine interrupts the query interrupt flag. After the CPU responds to an interrupt and enters the interrupt service routine, the global interrupt enable bit GIE is automatically cleared. The CPU does not respond to other interrupts during this period, nor can it form interrupt nesting.
Therefore, in the use of interrupts, the order of the query interrupt flags should be reasonably arranged to minimize the time the CPU stays in the interrupt service routine. When using the PIC series MCU to form the system, the number of interrupt sources should be minimized. For those events that take a long time to execute and do not need to use the interrupt mode, they should be processed as much as possible by querying the flags. For those who must use interrupts. The event handled by the method should try to query the interrupt flag of the event that is important to the system in the interrupt service program.
In addition, when exiting the interrupt service routine, only the processed interrupt flags are cleared, and all interrupt flags need not be cleared.
For the RB port level change interrupt, on the one hand, it is necessary to save the state of each change of the RB port, so as to judge which level of the line has changed at the next interruption; on the other hand, the mouth line for generating the interrupt can be set. The flag is executed by the query port line flag outside the interrupt service routine to reduce the CPU's stay in the interrupt service routine.
4 interrupt processing when the program spreads across pagesThe program memory space of the PIC series MCU is paged, and the size of each page space ranges from 512 bytes to 4k bytes. The page program counter PC is a 13-bit wide increment register whose lower 8-bit PCL is a read/write register whose high byte PCH (valid bit is 5 bits) cannot be directly read/write, it passes through a The 8-bit protection register PCLATH passes the upper 5 bits of the address to the high byte of the program counter. When an interrupt is responded, the breakpoint address in the PC is automatically protected by the push (PUSH); when the RETFIE instruction is executed, the breakpoint address in the stack is bounced back to the (POP) program memory PC.
Neither the push operation nor the pop operation affects the contents of the PCLATH register. At the same time, when the CPU responds to the interrupt and jumps to the interrupt entry address, it can only jump within this page without affecting the contents of the PLCATH register. In addition, the GOTO statement is arranged at the interrupt entry, and the GOTO statement can only be jumped on this page. When the interrupt service routine is stored in the first page of the program memory and the CPU is executing a program other than the first page, responding to the interrupt will cause the interrupt entry address and the interrupt return address to be incorrect and cause program confusion. The PIC16C65A is used to illustrate the solution to this problem.
The on-chip program memory of the PIC16C65A is 4k, divided into two pages, 2k per page. Assuming that the interrupt service routine is stored on the first page (0000H-07FFH), this is usually done because the interrupt entry address is on the first page, thus reducing the amount of program). Then, the specific procedure is as follows:
***************ORG 0000H0000H GOTO STARTORG 0004H***************0004H GOTO PRO-INTORG 0005H0005H START ............0234H PRO-INT ............RETFIE***************
Compiled by the assembler, the code stored in the program memory 0004H unit is 2A34H. When the CPU responds to the interrupt on the first page of the program memory, the program first jumps to 0004H, then jumps to 0234H to execute, normally enters the interrupt, and it can be normal after execution. return. When the CPU responds to the interrupt on the second page of the program memory, since the D4D3 (page select bit) of PCLATH is 01, the code when the CPU4 executes "GOTO PRO-INT" is 2A34H, but the program does not jump to 0234H, but jumps. Execute to 0A34H. Obviously, the program execution is wrong.
The solution to this problem is to arrange a program at program memory 0A34H, at the end of the interrupt program to determine the location of the program when the CPU responds to the interrupt, so that the program can properly set the page select bit according to the information, and then return to the interrupt.
******************ORG 0A34HBSF RAM,b ; Set the flag of the CPU response interrupt when the program is executed to the second page BCF PCLATH, 3; Switch the PC to the first page GOTO PRO-INT ; program jump to the interrupt service program ********************* The program should be added before the instruction RETFIE is as follows: ********* *********BTFSC RAM,b; Determine the position of the program before the CPU responds to the interrupt BSF PCLATH, 3; Set the page selection bit RETFIE******************
The RAM in the above program is a memory unit, b is a bit of the unit, this bit is cleared when the program is initialized, and the CPU is executing the program on the second page of the program memory and responding to the interrupt when the position is "1". After the above processing, the CPU can correctly enter the interrupt service routine and return the address before the interrupt correctly regardless of whether the first page or the second page of the program memory responds to the interrupt.
5 wake up the CPU with interruptsThe PIC series MCU has a sleep (SLEEP) power-saving mode. When a SLEEP instruction is executed, the chip enters a low-power sleep mode. After entering the sleep state, the main oscillator stops working, and the current consumed by the chip is extremely low (typically 1μA at 3V operating voltage and 32kHz clock). This feature is very beneficial for battery-powered systems. The interrupt can be used to wake up the CPU from sleep. These interrupt sources include external INT pin interrupts, RB port pin level change interrupts, and some peripheral interface interrupts. The CPU peripheral interface interrupts used to wake up the sleep state are: TMR1 interrupt, SSP start/stop bit detection interrupt, CCP capture mode interrupt, and slave parallel port read and write interrupts operating in asynchronous counter mode. Other peripheral interface interrupts cannot generate an interrupt due to the need for an on-chip Q clock.
Using the interrupt event to wake up the CPU is independent of the global interrupt enable bit GIE. Any interrupt can enable the interrupt source of position 1. As long as the interrupt is generated, the corresponding interrupt flag will be set to 1. The chip will stand in the state of the interrupt service routine and the global interrupt enable bit GIE. It is related to the instruction immediately following the SLEEP instruction. Since the PIC series MCU adopts a two-stage instruction pipeline structure, when the SLEEP instruction is executed, the next instruction is pre-fetched. Therefore, when the GIE bit is 0, the chip is woken up and the instruction fetched first is executed first; if the GIE bit is 1. After the chip is woken up, execute the pre-fetched instruction and then transfer to the interrupt entry address to execute the interrupt service routine. In this case, a null operation instruction NOP should be arranged after the SLEEP instruction so that the CPU can immediately enter the interrupt service routine after being woken up.
In short, the PIC series MCU is a kind of microcontroller with high performance and price ratio. Correct and reasonable use of its interrupt resources can make the system more perfect and work more stable.
KNB1-100 Miniature Circuit Breaker
KNB1-100 Mini Circuit breakers, also named as the air switch which have a short for arc extinguishing device. It is a switch role, and also is a automatic protection of low-voltage electrical distribution. Its role is equivalent to the combination of switch. Fuse. Thermal Relay and other electrical components. It mainly used for short circuit and overload protection. Generally, According to the poles, mini Circuit breaker can be divided into 1P , 1P+N , 2P, 3P and 4P.
KNB1-100 Miniature Circuit Breaker,Electronics Miniature Circuits Breaker,Automatic Miniature Circuit Breaker,Mini Circuit Breaker
Wenzhou Korlen Electric Appliances Co., Ltd. , https://www.zjaccontactor.com