Unstable circuit schematic of D flip-flop design

CSTLS5M00G56-A0-D

As shown in the figure is an unsteady circuit composed of D flip-flops. The unsteady circuit has no steady state and it automatically flips in two states 0 and 1.
Discharge quickly and prepare for the next charge. In addition, the high level of the Q terminal is charged to C2 through the resistor R2, so that the potential of the R terminal is gradually increased. After the time T2=0.69R2C2, the potential of the R terminal reaches the reset level VDD/2, so that the flip-flop turns over and the Q terminal becomes High level, Q end becomes low level. Complete an oscillation cycle. The above process is repeated repeatedly to form a self-oscillation.