In the hardware circuit design, this paper uses DSP chips and peripheral circuits to form a speed capture circuit. The motor drive controller uses a micro-control chip and peripheral circuits to form circuits for current sampling, overcurrent protection, and pressure regulation. The use of CPLD to achieve the brushless DC motor Logical commutation of the rotor position signal. In software design, the software realizes system control by combining C language and assembly language. Finally, a fuzzy control strategy for adjusting PID parameters is proposed.
1 IntroductionThe racing brake system is a relatively independent sub-system of the racing system. Its function is to bear the static weight and dynamic impact load of the racing car and absorb the kinetic energy when the racing car is braking, so as to realize the braking and control of the racing car. Its performance directly affects the fast reaction, safe braking and survivability of the car, which in turn affects the overall performance of the car. This paper designs the hardware and software of the all-electric anti-skid brake controller for racing cars, and finally studies the control law suitable for racing brakes.
2 System hardware circuit designThis racing car brake controller is composed of anti-skid controller and motor drive controller. Both controllers are based on DSP chips. The anti-skid controller is mainly based on the slip rate as the control object, outputting a given brake pressure, using the DSP chip as the CPU, plus racing and wheel speed signal conditioning circuits. The motor drive controller mainly adjusts the brake pressure and controls the motor current. It also uses the DSP chip as the CPU, plus the peripheral circuit motor current feedback conditioning circuit, overcurrent protection circuit, brake pressure conditioning circuit, and four groups of three-phase full bridges The inverter circuit, etc. constitute the motor drive controller.
2.1 The smallest system of DSP
The minimum system of DSP mainly involves memory expansion, JTAG interface configuration, reset circuit, ADC module setting, and clock circuit design.
1. External memory expansion.
The off-chip memory is to make up for the deficiencies of the DSP's internal RAM, while also taking into account that the program can be easily downloaded to the off-chip high-speed StaTIc RAM during the debugging process. The external static random access memory uses CY7C1041CV33. DSP can use on-chip program memory or off-chip program memory, which is determined by the pin XMP knife MC. JTAG interface. When the program needs to be debugged, the program download is completed through the JTAG interface, which is connected to the parallel port of the PC through the emulator.
2. Reset circuit and clock source module.
The resistance-capacitance circuit is used to generate the power-on reset and manual reset low-level reset circuit to generate the reset signal. A hardware watchdog is added, and its output terminal generates a reset signal WDRST. The two inputs of the power chip are both +5V, and the output is +1.9V and +3.3V to supply power to the DSP. The output power has two reset signals. When the power is unstable or too low, a reset signal will be generated.
3. The hardware configuration of the ADC module for analog-to-digital conversion.The analog-to-digital conversion ADC output voltage is 2V, and the output terminal is required to connect a ceramic capacitor with a low ESR capacity of 10μF to the analog ground. If the software is set in the external reference mode, ADCREFP can be connected to an external reference voltage of 2V and a low ESR capacitor with a capacitance of 1μF to 10μF. Otherwise, the accuracy of AD's internal reference source will be affected.
2.2 Speed ​​signal processing circuit of front wheel and brake wheel of racing car
The anti-skid controller of the racing car is mainly based on the slip rate as the control object to prevent the car from slipping. After the deviation of the slip rate is adjusted, the pressure reference value is output to track the given slip rate. The anti-skid controller must have a conditioning circuit for the speed signals of the front wheels of the racing car and the brake wheels, mainly to obtain the feedback slip rate. The racing speed signal is replaced by a free-rolling front wheel speed signal. Speed ​​sensors are installed on the front wheels and brake wheels of the racing car. When the wheels rotate, the speed sensors will generate AC signals in the form of sine waves. Each time the wheel rotates, the speed sensors will send out 50 cycles of sine AC signals. The amplitude of the sine AC signal changes with the wheel speed. The signal is a sine wave signal with a bias voltage of 2.5V, a peak value of 0.3V, and a maximum signal amplitude of not more than 5V. Convert this sine wave signal into a square wave with the same frequency and send it to the capture unit of the DSP to capture the count value interval ncapture of adjacent rising edges of the square wave, and then the wheel speed value V can be calculated. Since the CPUCLK is 150MHz, the capture time base is one of the timers, n is the frequency division coefficient of CPUCLK, and where it is the rolling radius of the wheel, the calculation formula of the wheel speed is:
The conditioning circuit is shown in Figure 1:
2.3 Logic signal circuit
The motor driver selects ALTERA's MAX7000A series devices to perform logical processing on signals such as the rotor position of the motor, and selects EPM7128AE with up to 76 programmable I/0 ports and 100 pins. This CPLD can meet the system design requirements. The device EPM7128AE realizes the three-phase full-bridge inverter circuit trigger signal of the motor, overcurrent protection, forward and reverse rotation, and three-phase full-bridge opening and closing functions. There are logic signals of two motors on a piece of CPLD device EPM7128AE. Since the output of the Hall position sensor CS3020 of the brushless DC motor is an open-collector structure, a 2KΩ resistor is pulled up, and then the Hall signals SA, SB, and SC are sent to the input port of the CPLD. The four terminals TMS, TCK, TDI, and TDO of the JTAG interface must be connected to a pull-up resistor, and then connected to a +5V power supply.
2.4 Power drive circuit of brushless DC motor
The power drive circuit of the brushless DC motor adopts a three-phase full-bridge inverter circuit composed of 6 N-channel MOSFETs centered on IR's dedicated drive chip IR2130. Its input is the PWM wave with the power ground as the ground, which is sent to the input port of IR2130, and the output controls the N-channel power drive tube MOSFET, thereby driving the brushless DC motor. The use of this driving method is mainly the clever use of the "bootstrap" technology to form a floating high-voltage side power supply by the power driver chip IR2130, which simplifies the design of the entire driving circuit and improves the reliability of the system. In addition, the IR2130 driver chip has built-in dead-zone circuits, as well as functions such as over-current protection and under-voltage protection, which greatly reduces the complexity of circuit design and further improves the reliability of the system.
2.5 Current sampling and overcurrent protection circuit
The current of the brushless DC motor is detected by the resistance on the bus of the power drive circuit. The resistor on the bus bar is connected in parallel by two 0.01Ω power resistors. The sampling circuit uses these two parallel sampling resistors for current sampling. The sampling resistor converts the current signal into a voltage signal, and the voltage signal is sent to the current monitoring chip for amplification , And then filtered by a second-order active filter circuit composed of OPA2344, and finally the current feedback signal is directly sent to the A/D converter.
The hardware overcurrent protection circuit plays an important role in the normal operation of the system, mainly for the protection of the power device MOSFET and the motor. The system also has a software protection function. The overcurrent signal OVCURX is sent to the input pin of the DSP. When OVCUR is high, the DSP will generate the motor control rotation signal ENABLE to turn off the logic signal to stop the motor. The chip IR2130 has its own overcurrent protection function.
2.6 Pressure signal amplifier circuit and its conditioning circuit
The pressure signal amplifier adopts a differential amplifier circuit for subtraction operation, with an ultra-low drift voltage operational amplifier as the core, and the amplification factor is 40 times. The amplifier is also equipped with zero adjustment and sensitivity adjustment functions. Among them, the chip 7809 provides the +9V voltage for the power chip 7660, and the chip 7660 changes the +9V voltage to -9V. These two voltages +9V and -9V provide power for the OP07 at the same time.
Since the voltage signal range from the voltage signal amplifier is +1V~+5V, and the reference voltage of the DSP A/D module is +3.3V, the maximum value of the sampled voltage signal cannot exceed +3.3V. Therefore, the voltage signal must be reduced to below +3.3v through a conditioning circuit. The conditioning circuit uses a precision operational amplifier OPA2344 to regulate the voltage signal from +1V to +5V to below +3V. The amplification factor needs to be set to 0.6 to facilitate DSP sampling.
3 Controller software designThe software of the racing brake controller is mainly based on C language, and assembly language is appropriately adopted. Such software writing brings convenience to the entire system software. C language speeds up the development of DSP programs, and greatly increases the readability and portability. Program debugging is performed in TI's C2000 Code Composer Studio (CCS) integrated development environment. Due to space limitations, only the system program initialization and main program flow are introduced here.
1. The system program is initialized.
Before the program of the system runs, the DSP clock source, timer, watchdog, AD module, I/O port, capture unit, interrupt, etc. must be initialized to make the system's internal resources, peripherals and hardware circuits Match. Before the system is running, all interrupts must be turned off to prevent unnecessary interrupts or program runaway when the program is running. Therefore, after the initialization, the system starts the interrupt to make the program run normally.
2. The main program flow of the system.
The main program of the racing full electric brake system includes program initialization module, timer interrupt service, analog timing sampling module, speed signal capture module, slip rate control module, pressure regulation module, current regulation module and so on. Among them, the timer interrupt service program provides a fixed clock trigger for the current, pressure, and slip rate modules, and this time is used as the adjustment reference for each module. When the program is running, first turn off the general interrupt of the system, complete the initialization, after receiving the brake command, turn on the general interrupt, and enter the infinite loop of program adjustment until the end of the program. The adjustment time of the current loop is the shortest and the response is the fastest. The adjustment time is related to the current signal filtering parameters, DSP sampling speed, CPU clock cycle, software filtering program, etc. The general time is a few milliseconds. The time of the pressure regulating ring is set to N times that of the current regulating ring. The adjustment times of the current regulating ring and the pressure regulating ring can be determined by measuring the regulating time on site, and the slip rate regulating time is longer. The main program flowchart of the system is shown as in Fig. 3.
Fuzzy controller is a key part of the application of fuzzy control in the control system. Its main process is to fuzzify the precise output of the controlled process in the control loop of the system and use it as the input of the fuzzy controller. The input and output of the fuzzy controller are actual accurate quantities. Then carry out fuzzy inference, establish linguistic fuzzy control rules internally, and judge the fuzzy output based on the input conditions. Finally, the amount of blur is converted into an actual accurate amount, that is, defuzzification. The specific process of fuzzy controller design is shown in Figure 4 below.
This article mainly completes the design of the racing brake control system, mainly hardware design, software design and control strategy research. The hardware design adopts high-speed DSP chip and CPLD and designs its peripheral circuits. The system also designed a drive circuit with IR2130 as the core, current signal hardware amplifying circuit, filter circuit and protection circuit, pressure signal amplifying circuit and filter circuit, racing speed and wheel speed processing circuit and so on. In terms of control strategy, fuzzy control is used to adjust PID parameters.
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