ISP image processing chip

1. Introduction to FH8510ISP processing chip

FH8510 is an image signal processing chip for CIS (CMOSImageSensor), which has a built-in powerful image processing engine, CMOS image sensor interface, TV encoder, D / A converter, provides NTSC / PAL output, and also provides ITU.BT65610Bit The output is mainly used in low-end standard definition analog CCTV cameras, car rear-view cameras and building intercom cameras. FH8510 can support a variety of CMOS image sensors, with low power consumption, high resolution, flexible configuration and high degree of customization. The default configuration of FH8510 can support OV7740, OV7725, and more CMOS image sensors can be configured through external EEPROM. FH8510 OSD uses hardware image data decompression technology, all OSD data can be placed in EEPROM. FH8510 provides an IRLED and IRCUT control interface, users can set the opening and closing threshold.

ISP image processing chip

2. Internal block diagram of FH8510

ISP image processing chip

2.1, video input

Support SVGA, D1, VGA input

RGBBayer

Maximum data bit width 10-bit

Configurable clock positive and negative edge sampling

Frame valid and line valid signal polarity can be configured

Maximum pixel clock 54MHz

2.2, image processing (ISP)

RGBBayer data format, arbitrary coordinates of Sensor output window

Automatic color to black and white

Fixed pattern noise cancellation

Automatic detection and elimination of dead pixels

Sensor column fixed mode noise cancellation (external 4KBEEPROM)

Vignette compensation (LensShadeCorrecTIon)

Configurable lens center position

The compensation coefficient table is configurable

Automatic black matrix elimination

Adaptive 2D denoising

Image information statistics

Configurable number, position and size of statistical windows

The maximum number of statistical windows is 64

Provide maximum, minimum and average values ​​for each window

Automatic exposure, 50Hz / 60Hz flicker elimination

Automatic white balance

CFA interpolation based on edge detection

Automatic color correction, realizing configurable color space conversion RGB2RGB

Gamma correction, Gamma table is configurable

Image enhancement

Contrast, hue and saturation adjustment

Image sharpening (5x5 filtering, intensity can be configured)

Image zoom

Configurable scaling core, support stepless scaling, matching Sensor output format and SD format

Configurable horizontal and vertical scaling

Support 64 phases, the initial phase is independently configurable

Image Resolution

VGASensor, 420TVL

D1, SVGASensor, 540TVL

2.3, video output

Composite video CVBS (NTSC720 & TImes; 480PAL720 & TImes; 576)

ITU.BT-656 (10Bit) output (optional)

2.4, OSD

1 Graphic layer overlay (external 8KEEPROM)

Graphic window position can be configured

Graphic window height and width can be configured

Graphic data format can be configured (support lossless compression 1 ~ 6bpp index bitmap)

Palette content is configurable, supports up to 64 colors 32bit palette (ARGB8888 format)

Hardware flashing display control

Hardware Graphic data decompression

Hardware Graphic data DMA transfer handshake

2.5, clock

6MHz crystal

2.6, EEPROM configuration

2KBYTE supports multiple CMOS image sensor configurations

4KBYTE supports multiple CMOS image sensor configurations and column fixed mode noise cancellation

8KBYTE supports multiple CMOS image sensor configurations, column fixed mode noise cancellation, OSD

3. Typical applications

The occasions that can be used include building intercom, security monitoring, and rear view system, as shown in the following block diagram:

ISP image processing chip

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