FPGA design ideas, the principle of speed and area interchange can not be ignored

Speed ​​and area interchange principle. High data throughput can be achieved by changing the area. In fact, serial /parallel conversion is an idea of ​​changing the area by area.

2. Ping pong operation.

3. The idea of ​​string/parallel conversion.

One of the important skills of high speed data processing. Here I will give an example of polyphase filter extraction:

After the extraction, the two channels of data can be processed at a rate of two.

4. Pipeline design ( excellent in the fir filter, one clock outputs one data)

Pipeline design can increase system frequency to some extent. . The premise is that the design can be divided into several steps for processing, and the whole data processing process is one-way, that is, there is no feedback or inverse operation, and the output of the previous step is the input of the next step. . .

5. Logical replication and module multiplexing.

Module reuse is very widely used to save logic resources (for example)

Contrast, not much to say, one case is worth a thousand words!

As for the logical copy, I will not know it yet. Copy the concept first: Logical replication is an optimization method that improves the timing conditions by increasing the area. The most important application is to adjust the fanout of the signal. In other words, that is, its fanout is very large, so in order to increase the driving ability of this signal, it is necessary to insert many levels of Buffer, which increases the path delay of this signal to some extent. In this case, the logic for generating this signal can be assigned, and the subsequent circuits are driven by the signals of the same frequency and the same phase. The average fan-out is low to each fan, so that the need to insert the Buffer can satisfy the increase of the driving capability. , thereby saving the path delay of the signal.

In short. Module multiplexing saves area and sacrifices speed, while logical copying is just the opposite. .

6. Modular design

It is a top-down design approach. . Not discussed, very simple and hard to get things.

7. Clock design skills

Try to avoid using the clock generated by the FPGA's internal logic because it can easily cause problems with function or timing. The clock generated by the internal combinatorial logic is prone to glitch, affecting the functional realization of the design; the inherent delay of the combinatorial logic is also prone to timing problems.

If the output generated by the internal combinational logic is used as a clock signal or an asynchronous reset signal, glitch may inevitably occur. If the signal is now in the process of transformation, it will violate the setup time and hold time requirements, thereby affecting the output state of subsequent circuits, and even causing the entire system to fail.

If you want to reduce the glitch, it is best to use the clock to hit it. . Achieve the effect of synchronization processing.

For the divided clocks that are needed in the design, the enable clock should be used as much as possible to allow the divided signal to be used as an enable signal.